Conventionally, a flip-flop circuit of a semiconductor integrated circuit that operates at high speeds, i.e., clock frequencies of 100 MHz or above, has been constructed as described below.
FIG. 6 is a diagram showing the circuit of a conventional ECL master-slave type flip-flop circuit 7.
In FIG. 6, the flip-flop circuit 7 comprises npn transistors Q'1-Q'19, 71-89, resistors R'1-R'4, 91-94 and a power source 95.
The transistors 71-74,79,80 form a master D flip-flop (D-FF).
The transistors 75-78,81,82 form a slave D flip-flop D-FF.
Of these transistors, the transistors 79-82 function as the current switches for switching the current paths of respectively corresponding transistors which respond to the clock signals according to their logic values.
The transistors 83-86,89 form the constant current sources of respective master D flip-flops D-FFs.
In FIG. 6, each symbol attached to each terminal indicates the names of that terminal and signal, with a horizontal overbar indicating the logical negation (reversal) of a signal.
The operation of the master D flip-flop D-FF is as described below.
When a logic value 0 (voltage value L) is input to a non-inverting clock input terminal (CK) while a logic value 1 (voltage value H) is input to an inverting clock input terminal, transistor enters a nonconducting state (turns off), and transistor 87 enters a conductive state (turns on). In the wake of the above, transistor 80 turns off, and the transistor 79 turns on. In the case, when the non-inverting input terminal D has a logic value of 1 and the inverting input terminal has a logic value of 0, transistor 71 turns on, and transistor 72 turns off.
Accordingly, in FIG. 6, a attains a logic value of 0, and b attains a logic value of 1.
In this case, when the transistor 80 is off, current is not supplied to the transistors 73,74.
In this state, when the non-inverting clock input terminal attains a logic value of 1 and the inverting clock input terminal attains a logic value of 0, the transistor 87 turns off, transistor 88 turns on, transistor 79 turns off, and the transistor 80 turns on.
Therefore, transistors 71,72 enter the state of not having a current supply while transistors 73,74 enter the state of having a current supply.
In this case, because, as mentioned above, a shown in FIG. 6 has a logic value of 0 while b therein has a logic value of 1, transistor 74 turns off, and the transistor 73 turns on.
Consequently, a, to which the collector of transistor 73 is connected, retains a logic value of 0, and b, to which the collector of transistor 74 is connected, retains a logic value of 1.
As has been mentioned above, in a and b in FIG. 6, the values of the inverted input terminal and non-inverting input terminal are saved immediately before the non-inverting clock input terminal attains a logic value of 1 and the inverting clock input terminal attains a logic value of 0 are maintained, respectively.
This operation is common to the slave D flip-flops D-FFs.
The flip-flop circuit 7 is constructed to connect the master D flip-flop D-FF and slave D flip-flop D-FF by ECL circuit as mentioned above in series, in a manner that the clock signals input to them are equivalently logically inverted. In this way, it forms the master-slave flip-flop D-FF.
The flip-flop circuit 7 mentioned above is, from the standpoint of the method for the configuration of a master-slave D-flip-flop, quite a general circuit.
However, for the uses at clock frequencies of 100 MHz or above to which the flip-flop circuit is applied, general CMOS logic circuits cannot be employed.
The reason for this is that when a general CMOS circuit is used, too much power is consumed.
In the master-slave D-flip-flop constituted by the ECL circuit described in the prior art, because two transistors are connected in series between the power source and ground, a supply voltage of at least twice that between the base and emitter of a transistor is required. In other words, at least about 1.2 V is necessary for the supply voltage. In addition, there is the problem that 1.8 V or more must be supplied to enable the master-slave D flip-flop to perform in a stable manner in actual operation.
To operate logic circuits, such as flip-flops, stably at low voltage is important, for example, in the field of small size mobile transmitters.
For reducing the size of mobile transmitters, it is indispensable to reduce the size of the battery to be used.
Batteries normally used for mobile transmitters are auxiliary batteries, such as nickel-cadmium batteries, and the starting power of a single unit is usually at the level of 1 V.
For the circuits as shown in the prior art, the development has proceeded with size reduction as one of the most preferential objects, but this is not applicable to a device using a general auxiliary battery in a single unit as the power source.
It is an object of the present invention to provide a logic circuit for implementing flip-flops, etc., that is capable of operating stably and at high speed at a low supply voltage of about 1 V.